1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which not only has a redundant memory cell for the purpose of replacing defective cells, but also has a mode in which address positions are accessed by means of instructions from an external address signal, and a mode in which internally generated address positions are accessed in accordance with prescribed data.
2. Description of the Related Art
In a semiconductor memory device, because of the nature of the manufacturing process, it is difficult to achieve a zero level of defective cells. Because classification of a chip in which defective cells have occurred as a bad chip would lower the manufacturing yield, the general approach is to apply redundancy technology, in which spare memory cells known as redundancy memory cells are provided beforehand, these being exchanged for defective memory cells occurring in the normal memory cell array, enabling the device to be used as a good chip, thereby improving the yield.
Semiconductor memory devices have a variety of operating modes. In a DRAM, for example, it is necessary to perform a refresh operation at a prescribed interval in order to refresh the contents of the memory, and while in the past the refresh address signal required for the refresh operation was externally input, to reduce the number of external components, in recent years it has become common to have an internal refresh address signal generating circuit to generate the refresh address. To perform a refresh operation in a DRAM having such an internal refresh address generating circuit, an externally input control signal is set to a state which differs from the state in the normal mode, the DRAM sensing the difference in the state of this control signal and performing the refresh operation. Therefore, the DRAM has a circuit which distinguishes between the normal mode and the refresh mode.
Additionally, DRAMs have special modes known as burst modes or nibble modes, in which data from a number of continuous addresses are read out at high speed. In these modes, a number of bits are continuously read out by internally generating continuous addresses with respect to an address externally specified at a given cycle.
In a semiconductor memory device making use of redundancy technology and also having various operating modes, a three-stage operation occurs, in which the mode switching circuit first determines the mode from the clock signal and the control signals such as the/CAS signal, after which an address switching circuit selects, depending upon the mode, either the external address or the internally generated address, followed by a determination being made by a redundancy determining circuit as to whether the address selected by the address switching circuit is an exchanged address.
In a semiconductor memory device, to raise the manufacturing yield, it is desired to improve the operating speed. To improve the operating speed, a synchronous DRAM of the type described above has been proposed, and in the operational flow of semiconductor memory devices in the past, the determination of the operating mode followed by a determination of redundancy. Therefore, the time actually required to achieve access is the total of the mode determining time, the address switching time, and the redundancy determining time, making it necessary to shorten these times in order to improve the operating speed of the semiconductor memory device.
In this regard, Japanese Unexamined Patent Application Publication No. 2-83899 discloses a semiconductor memory device which, in a serial access memory, by performing a redundancy determination on the serial access address on previous cycle, the operating speed in the serial access mode is improved. However, because conventional operation is performed in the normal mode, it was not possible with this device to improve the operating speed in the normal mode.